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1 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier march 2006 2006 integrated device technology, inc. dsc 5173/12 c commercial and industrial temperature ranges the idt logo is a registered trademark of integrated device technology, inc. features: ? phase-lock loop clock distribution for applications ranging from 10mhz to 133mhz operating frequency ? distributes one clock input to two banks of four outputs ? separate output enable for each output bank ? external feedback (fbk) pin is used to synchronize the outputs to the clock input ? output skew <200 ps ? low jitter <200 ps cycle-to-cycle ? 1x, 2x, 4x output options (see table): ? idt2308-1 1x ? idt2308-2 1x, 2x ? idt2308-3 2x, 4x ? idt2308-4 2x ? idt2308-1h, -2h, and -5h for high drive ? no external rc network required ? operates at 3.3v v dd ? available in soic and tssop packages functional block diagram description: the idt2308 is a high-speed phase-lock loop (pll) clock multiplier. it is designed to address high-speed clock distribution and multiplication applica- tions. the zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133mhz. the idt2308 has two banks of four outputs each that are controlled via two select addresses. by proper selection of input addresses, both banks can be put in tri-state mode. in test mode, the pll is turned off, and the input clock directly drives the outputs for system testing purposes. in the absence of an input clock, the idt2308 enters power down, and the outputs are tri-stated. in this mode, the device will draw less than 25 a. the idt2308 is available in six unique configurations for both pre- scaling and multiplication of the input ref clock. (see available options table.) the pll is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. the idt2308 is characterized for both industrial and commercial operation. idt2308 3.3v zero delay clock multiplier pll s1 2 14 15 3 clka1 clka2 clka3 clka4 6 10 11 clkb1 clkb2 clkb3 clkb4 9 fbk 16 control logic 7 8 1 ref s2 (-2, -3) (-3, -4) (-5) 2 2 2
2 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier pin configuration soic/ tssop top view ref clka1 s2 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 clka2 gnd clkb1 fbk clka4 gnd s1 v dd v dd clkb2 clkb3 clkb4 clka3 symbol rating max. unit v dd supply voltage range ?0.5 to +4.6 v v i (2) input voltage range (ref) ?0.5 to +5.5 v v i input voltage range ?0.5 to v (except ref) v dd +0.5 i ik (v i < 0) input clamp current ?50 ma i ok terminal voltage with respect 50 ma (v o < 0 or v o > v dd ) to gnd (inputs v ih 2.5, v il 2.5) i o continuous output current 50 ma (v o = 0 to v dd ) v dd or gnd continuous current 100 ma t a = 55c maximum power dissipation 0.7 w (in still air) (3) t stg storage temperature range ?65 to +150 c operating commercial temperature 0 to +70 c temperature range operating industrial temperature -40 to +85 c temperature range notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils. applications: ? sdram ? telecom ? datacom ? pc motherboards/workstations ? critical path delay designs pin number functional description ref (1) 1 input reference clock, 5 volt tolerant input clka1 (2) 2 clock output for bank a clka2 (2) 3 clock output for bank a v dd 4 3.3v supply gnd 5 ground clkb1 (2) 6 clock output for bank b clkb2 (2) 7 clock output for bank b s2 (3) 8 select input, bit 2 s1 (3) 9 select input, bit 1 clkb3 (2) 10 clock output for bank b clkb4 (2) 11 clock output for bank b gnd 12 ground v dd 13 3.3v supply clka3 (2) 14 clock output for bank a clka4 (2) 15 clock output for bank a fbk 16 pll feedback input notes: 1. weak pull down. 2. weak pull down on all outputs. 3. weak pull ups on these inputs. pin description absolute maximum ratings (1)
3 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier device feedback from bank a frequency bank b frequency idt2308-1 bank a or bank b reference reference idt2308-1h bank a or bank b reference reference idt2308-2 bank a reference reference/2 idt2308-2 bank b 2 x reference reference idt2308-2h bank a reference reference/2 idt2308-2h bank b 2 x reference reference idt2308-3 bank a 2 x reference reference or reference (1) idt2308-3 bank b 4 x reference 2 x reference idt2308-4 bank a or bank b 2 x reference 2 x reference idt2308-5h bank a or bank b reference/2 reference/2 note: 1. output phase is indeterminant (0 or 180 from input clock). available options for idt2308 s2 s1 clk a clk b output source pll shut down l l tri-state tri-state pll y l h driven tri-state pll n h l driven driven ref y h h driven driven pll n function table (1) select input decoding note: 1. h = high voltage level l = low voltage level
4 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier zero delay and skew control to close the feedback loop of the idt2308, the fbk pin can be driven from any of the eight available output pins. the output dr iving the fbk pin will be driving a total load of 7pf plus any additional load that it drives. the relative loading of this output (with respect to th e remaining outputs) can adjust the input-output delay. for applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. if input-output delay adjustments are required, use the output load difference chart to calculate loading differences between the feedback output and remaining outputs. ensure the outputs are loaded equally, for zero output-output skew. ref to clka/clkb delay vs. output load difference between fbk pin and clka/clkb pins ref to clka/clkb delay (ps) output load difference between fbk pin and clka/clkb pins ( pf) 1500 1000 500 0 -500 -1000 -1500 -30 -25 -20 -15 -10 -5 05 10 15 20 25 30
5 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier note: 1. applies to both ref and fbk. dc electrical characteristics - commercial symbol parameter conditions min. typ. (1) max. unit v il input low voltage level ? ? 0.8 v v ih input high voltage level 2 ? ? v i il input low current v in = 0v ? ? 50 a i ih input high current v in = v dd ? ? 100 a v ol output low voltage i ol = 8ma (-1, -2, -3, -4) ? ? 0.4 v i ol = 12ma (-1h, -2h, -5h) v oh output high voltage i oh = -8ma (-1, -2, -3, -4) 2.4 ? ? v i oh = -12ma (-1h, -2h, -5h) i dd_pd power down current ref = 0mhz (s2 = s1 = h) ? ? 12 a 100mhz clka (-1, -2, -3, -4) ? ? 45 100mhz clka (-1h, -2h, -5h) ? ? 70 i dd supply current unloaded outputs 66mhz clka (-1, -2, -3, -4) ? ? 32 ma select inputs at v dd or gnd 66mhz clka (-1h, -2h, -5h) ? ? 50 33mhz clka (-1, -2, -3, -4) ? ? 18 33mhz clka (-1h, -2h, -5h) ? ? 30 symbol parameter test conditions min. max. unit v dd supply voltage 3 3.6 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance below 100mhz ? 30 pf load capacitance from 100mhz to 133mhz ? 15 pf c in input capacitance (1) ?7pf operating conditions- commercial
6 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier switching characteristics - commercial symbol parameter conditions min. typ. max. unit t 1 output frequency 30pf load, all devices 10 ? 100 mhz t 1 output frequency 20pf load, -1h, -2h, -5h devices (1) 10 ? 133.3 m h z t 1 output frequency 15pf load, -1, -2, -3, -4 devices 10 ? 133.3 m h z duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % (-1, -2, -3, -4, -1h, -2h, -5h) 30pf load duty cycle = t 2 t 1 measured at 1.4v, f out = 50mhz 45 50 55 % (-1, -2, -3, -4, -1h, -2h, -5h) 15pf load t 3 rise time (-1, -2, -3, -4) measured between 0.8v and 2v, 30pf load ? ? 2.2 ns t 3 rise time (-1, -2, -3, -4) measured between 0.8v and 2v, 15pf load ? ? 1.5 ns t 3 rise time (-1h, -2h, -5h) measured between 0.8v and 2v, 30pf load ? ? 1.5 ns t 4 fall time (-1, -2, -3, -4) measured between 0.8v and 2v, 30pf load ? ? 2.2 ns t 4 fall time (-1, -2, -3, -4) measured between 0.8v and 2v, 15pf load ? ? 1.5 ns t 4 fall time (-1h, -5h) measured between 0.8v and 2v, 30pf load ? ? 1.25 ns t 5 output to output skew on same bank all outputs equally loaded ? ? 200 ps (-1, -2, -3, -4) output to output skew (-1h, -2h, -5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b (-1, -4, -2h, -5h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-2, -3) all outputs equally loaded ? ? 400 ps t 6 delay, ref rising edge to fbk rising edge measured at v dd /2 ? 0 250 ps t 7 device to device skew measured at v dd /2 on the fbk pins of devices ? 0 700 ps t 8 output slew rate measured between 0.8v and 2v on -1h, -2h, -5h 1 ? ? v/ns device using test circuit 2 t j cycle to cycle jitter measured at 66.67 mhz, loaded outputs, 15pf load ? ? 200 (-1, -1h, -4, -5h) measured at 66.67 mhz, loaded outputs, 30pf load ? ? 200 ps measured at 133.3 mhz, loaded outputs, 15pf load ? ? 100 tj cycle to cycle jitter measured at 66.67 mhz, loaded outputs, 30pf load ? ? 400 ps (-2, -2h, -3) measured at 66.67 mhz, loaded outputs, 15pf load ? ? 400 t lock pll lock time stable power supply, valid clocks presented ? ? 1 ms on ref and fbk pins note: 1. idt2308-5h has maximum input frequency of 133.33 mhz and maximum output of 66.67mhz.
7 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier note: 1. applies to both ref and fbk. dc electrical characteristics - industrial symbol parameter conditions min. typ. (1) max. unit v il input low voltage level ? ? 0.8 v v ih input high voltage level 2 ? ? v i il input low current v in = 0v ? ? 50 a i ih input high current v in = v dd ? ? 100 a v ol output low voltage i ol = 8ma (-1, -2, -3, -4) ? ? 0.4 v i ol = 12ma (-1h, -2h, -5h) v oh output high voltage i oh = -8ma (-1, -2, -3, -4) 2.4 ? ? v i oh = -12ma (-1h, -2h, -5h) i dd_pd power down current ref = 0mhz (s2 = s1 = h) ? ? 25 a 100mhz clka (-1, -2, -3, -4) ? ? 45 100mhz clka (-1h, -2h, -5h) ? ? 70 i dd supply current unloaded outputs 66mhz clka (-1, -2, -3, -4) ? ? 32 ma select inputs at v dd or gnd 66mhz clka (-1h, -2h, -5h) ? ? 50 33mhz clka (-1, -2, -3, -4) ? ? 18 33mhz clka (-1h, -2h, -5h) ? ? 30 symbol parameter test conditions min. max. unit v dd supply voltage 3 3.6 v t a operating temperature (ambient temperature) -40 +85 c c l load capacitance below 100mhz ? 30 pf load capacitance from 100mhz to 133mhz ? 15 pf c in input capacitance (1) ?7pf operating conditions- industrial
8 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier switching characteristics - industrial symbol parameter conditions min. typ. max. unit t 1 output frequency 30pf load, all devices 10 ? 100 m h z t 1 output frequency 20pf load, -1h, -2h, -5h devices (1) 10 ? 133.3 m h z t 1 output frequency 15pf load, -1, -2, -3, -4 devices 10 ? 133.3 m h z duty cycle = t 2 t 1 measured at 1.4v, f out = 66.66mhz 40 50 60 % (-1, -2, -3, -4, -1h, -2h, -5h) 30pf load duty cycle = t 2 t 1 measured at 1.4v, f out = 50mhz 45 50 55 % (-1, -2, -3, -4, -1h, -2h, -5h) 15pf load t 3 rise time (-1, -2, -3, -4) measured between 0.8v and 2v, 30pf load ?? 2.2 ns t 3 rise time (-1, -2, -3, -4) measured between 0.8v and 2v, 15pf load ?? 1.5 ns t 3 rise time (-1h, -2h, -5h) measured between 0.8v and 2v, 30pf load ?? 1.5 ns t 4 fall time (-1, -2, -3, -4) measured between 0.8v and 2v, 30pf load ?? 2.5 ns t 4 fall time (-1, -2, -3, -4) measured between 0.8v and 2v, 15pf load ?? 1.5 ns t 4 fall time (-1h, -5h) measured between 0.8v and 2v, 30pf load ?? 1.25 ns t 5 output to output skew on same bank all outputs equally loaded ?? 200 ps (-1, -2, -3, -4) output to output skew (-1h, -2h, -5h) all outputs equally loaded ?? 200 ps output bank a to output bank b (-1, -4, -2h, -5h) all outputs equally loaded ?? 200 ps output bank a to output bank b skew (-2, -3) all outputs equally loaded ?? 400 ps t 6 delay, ref rising edge to fbk rising edge measured at v dd /2 ? 0 250 ps t 7 device to device skew measured at v dd /2 on the fbk pins of devices ? 0 700 ps t 8 output slew rate measured between 0.8v and 2v on -1h, -2h, -5h 1 ?? v/ns device using test circuit 2 t j cycle to cycle jitter measured at 66.67 mhz, loaded outputs, 15pf load ?? 200 (-1, -1h, -4, -5h) measured at 66.67 mhz, loaded outputs, 30pf load ?? 200 ps measured at 133.3 mhz, loaded outputs, 15pf load ?? 100 tj cycle to cycle jitter measured at 66.67 mhz, loaded outputs, 30pf load ?? 400 ps (-2, -2h, -3) measured at 66.67 mhz, loaded outputs, 15pf load ?? 400 t lock pll lock time stable power supply, valid clocks presented ?? 1ms on ref and fbk pins note: 1. idt2308-5h has maximum input frequency of 133.33 mhz and maximum output of 66.67mhz.
9 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier output 1.4v t5 1.4v output input t6 v dd /2 fbk v dd /2 t7 v dd /2 fbk, device 2 v dd /2 fbk, device 1 1.4v 1.4v t2 t1 1.4v 2v 0.8v t3 t4 0.8v 3.3v 0v 2v output switching waveforms duty cycle timing all outputs rise/fall time output to output skew input to output propagation delay device to device skew
10 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier typical duty cycle (1) and i dd trends (2) for idt2308-1, 2, 3, and 4 notes: 1. duty cycle is taken from typical chip measured at 1.4v. 2. i dd data is calculated from i dd = icore + ncvf, where icore is the unloaded current (n = number of outputs; c = capacitance load per output (f); v = voltage s upply(v); f = frequency (hz). 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd (v) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs v dd (for 30pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz d u t y c y c l e ( % ) 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd (v) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs v dd (for 15pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz 20 40 60 80 100 120 140 frequency (mhz) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs frequency (for 30pf loads over temperature - 3.3v) -40c 0c 25c 70c 85c d u t y c y c l e ( % ) d u t y c y c l e ( % ) 133mhz 20 40 60 80 100 120 140 frequency (mhz) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs frequency (for 15pf loads over temperature - 3.3v) -40c 0c 25c 70c 85c d u t y c y c l e ( % ) 02 4 6 8 number of loaded outputs 0 20 40 60 80 100 120 140 i dd vs number of loaded outputs (for 30pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz i d d ( m a ) 02 4 6 8 number of loaded outputs 0 20 40 60 80 100 120 140 i dd vs number of loaded outputs (for 15pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz i d d ( m a )
11 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier typical duty cycle (1) and i dd trends (2) for idt2308-1h, -2h, and -5h notes: 1. duty cycle is taken from typical chip measured at 1.4v. 2. i dd data is calculated from i dd = icore + ncvf, where icore is the unloaded current (n = number of outputs; c = capacitance load per output (f); v = voltage s upply(v); f = frequency (hz). 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd (v) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs v dd (for 30pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz d u t y c y c l e ( % ) 3 3.1 3.2 3.3 3.4 3.5 3.6 v dd (v) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs v dd (for 15pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz 20 40 60 80 100 120 140 frequency (mhz) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs frequency (for 30pf loads over temperature - 3.3v) -40c 0c 25c 70c 85c d u t y c y c l e ( % ) d u t y c y c l e ( % ) 133mhz 20 40 60 80 100 120 140 frequency (mhz) 40 42 44 46 48 50 52 54 56 58 60 duty cycle vs frequency (for 15pf loads over temperature - 3.3v) -40c 0c 25c 70c 85c d u t y c y c l e ( % ) 02 4 6 8 number of loaded outputs 0 20 40 60 80 100 120 140 i dd vs number of loaded outputs (for 30pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz i d d ( m a ) 02 4 6 8 number of loaded outputs 0 20 40 60 80 100 120 140 i dd vs number of loaded outputs (for 15pf loads over frequency - 3.3v, 25c) 33mhz 66mhz 100mhz i d d ( m a ) 160 160
12 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier test circuits test circuit 1 test circuit 1 test circuit for all parameters except t8 test circuit for t8, output slew rate on -1h, -2h, and -5h device v dd outputs clk out c load v dd gnd gnd 0.1 f 0.1 f v dd outputs 10pf v dd gnd gnd 0.1 f 0.1 f 1k 1k clk out
13 commercial and industrial temperature ranges idt2308 3.3v zero delay clock multiplier ordering information idt xxxxx xx x package process device type blank i 2308-1 2308-2 2308-3 2308-4 2308-1h 2308-2h 2308-5h commercial (0 o c to +70 o c) industrial (-40 o c to +85 o c) zero delay clock buffer with standard drive dc dcg pg pgg small outline soic - green thin shrink small outline package tssop - green zero delay clock buffer with high drive } } corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 clockhelp@idt.com san jose, ca 95138 fax: 408-284-2775 www.idt.com

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